In one conventional arrangement, a frame is transmitted from a first device to a second device. Prior to transmitting the frame, the first device inserts into the frame a Cyclic Redundancy Check (CRC) value calculated from a portion of the frame. After the second device receives the frame, the second device re-generates the CRC value from that same portion of the frame (as received by the second device), and compares this re-generated CRC value to the CRC value inserted in the frame by the first device to determine whether error is present in the portion of the frame (as received by the second device).
In this conventional arrangement, CRC computation is based on interpreting a stream of bits as coefficients of a polynomial. For example, in this conventional arrangement, the stream “1010” corresponds to a polynomial of (1x3)+(0x2)+(1x1)+(0 x0) or, more simply, x3+x1. This polynomial is divided by another polynomial known as the modulus. By way of simplistic example, the other polynomial may be “11” or x+1. The CRC value is calculated as the remainder of a division of the bit stream polynomial by the modulus. CRC polynomial division, however, is somewhat different from ordinary division in that it is done according to the carry-less mathematics of the finite field GF(2), in which, e.g., even number coefficients become zeroes and odd number coefficients become ones. As can be readily appreciated, the computations involved in determining CRC values increases processing overhead in this conventional arrangement.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly.